A. Field of the Invention
The present invention relates to a method for producing a semiconductor device.
B. Description of the Related Art
In recent years, a matrix converter has been known as a direct-link-type conversion circuit which does not require a direct current (DC) smoothing circuit including, for example, an electrolytic capacitor or a DC reactor, in a power conversion circuit that performs alternating current (AC)/AC conversion, AC/DC conversion, and DC/AC conversion using a semiconductor element. Since the matrix converter is used at an AC voltage, a plurality of switching devices forming the matrix converter require a bidirectional switching device which can control a current in the forward direction and the reverse direction.
In recent years, a bidirectional switching device has been proposed in terms of reducing the size and weight of a circuit, improving efficiency and response, and reducing costs. In this device, two reverse blocking insulated gate bipolar transistors (IGBTs) are connected in inverse parallel to each other, as illustrated in the equivalent circuit diagram of FIG. 10. FIG. 10 is a circuit diagram illustrating the equivalent circuit of the bidirectional switching device using the reverse blocking IGBT. The inverse parallel connection structure of the reverse blocking IGBTs has an advantage that a diode for blocking a reverse voltage is not required. That is, the reverse blocking IGBT means a device which equalizes the reverse breakdown voltage to the forward breakdown voltage and has high reliability of breakdown voltage. In the general IGBT which is used in the power conversion circuit according to the related art, an effective reverse breakdown voltage is not required, similarly to the general transistor or insulated gate field effect transistor (MOSFET) without a reverse breakdown voltage. Therefore, an IGBT which has a reverse breakdown voltage lower than the forward breakdown voltage and has a low reliability of breakdown voltage is sufficient for the bidirectional switching device.
Next, the structure of the reverse blocking IGBT according to the related art will be described. FIG. 9 is a cross-sectional view schematically illustrating the cross-sectional structure of the reverse blocking IGBT according to the related art. FIG. 9 is described in the following JP 2006-80269 A. The reverse blocking IGBT according to the related art has a structure in which an active region 110 is provided at the center, a breakdown voltage structure region 120 is provided in an outer circumferential portion surrounding the active region 110, and a p-type separation layer 31 is provided so as to surround the outer circumference of the breakdown voltage structure region 120. Therefore, the depth of the p-type separation layer 31 needs to be very large in order to form the p-type separation layer 31 using only thermal diffusion from one main surface of a semiconductor substrate, and a high-temperature and long-term thermal diffusion (drive-in) process is involved.
The active region 110 illustrated in FIG. 9 is a main current path of a vertical IGBT including, for example, an n− drift region 1, a p-type base region 2, an n+ emitter region 3, a gate insulating film 4, a gate electrode 5, an interlayer insulating film 6, an emitter electrode 9, a p-type collector region 10, and a collector electrode 11. The p-type separation layer 31 is a p-type region which is formed by the thermal diffusion of boron (B) at a depth that extends from the front surface of the semiconductor substrate to the p-type collector region 10 provided on the rear surface side. A termination portion of a pn junction surface between the p-type collector region 10 and the n− drift region 1, which is a reverse breakdown voltage junction, is not exposed from a side end surface 12 of a chip, which is a cutting surface during chipping, by the p-type separation layer 31, but it is exposed from a surface 13 of the breakdown voltage structure region 120 that is protected by an insulating film. Therefore, the reverse blocking IGBT including the p-type separation layer 31 can improve the reliability of the reverse breakdown voltage.
FIG. 6A to 6D and FIG. 7A to 7D are cross-sectional views sequentially illustrating the producing steps of an impurity diffusion process for forming a p-type separation layer 104 of the reverse blocking IGBT using coating diffusion and ion implantation, respectively. FIG. 6 is a cross-sectional view illustrating the state of the separation layer which is being formed by coating diffusion according to the related art. FIG. 7 is a cross-sectional view illustrating the state of the separation layer which is being formed by ion implantation according to the related art. FIG. 8 is a cross-sectional view illustrating the end structure of a reverse blocking IGBT according to the related art. FIG. 8(a) illustrates the reverse blocking IGBT in which a separation layer is formed by the diffusion layer that is formed by the producing steps illustrated in FIGS. 6 and 7 so as to pass through a semiconductor substrate. First, a thermally-oxidized film 101 with a thickness of about 1.5 μm to 2.5 μm is formed as a dopant mask on the front surface of a semiconductor substrate 100 with a large thickness of 600 μm or more which is made of silicon (Si) as a semiconductor material (FIG. 6A and FIG. 7A).
The thermally-oxidized film 101 is patterned to form an opening portion 102 which introduces impurities for forming the separation layer (FIG. 6B and FIG. 7B). A boron source 103, which is impurities, is coated on the opening portion 102 to form a shallow boron deposit layer (or boron ion implantation 105 is performed for a portion of the semiconductor substrate 100 which is exposed through the opening portion 102 of the thermally-oxidized film 101) (FIG. 6C and FIG. 7C). The thermally-oxidized film 101 which is used as a dopant mask for the selective diffusion of boron (diffusion for the p-type separation layer) is removed. A heat treatment is performed at a high temperature (1300° C.) for a long time (100 hours to 200 hours) to form the p-type diffusion layer 104 with a depth of about 100 μm to 200 μm (FIG. 6D and FIG. 7D). The p-type diffusion layer 104 is used as the separation layer.
Then, a process (not illustrated) of forming an oxide film on the front surface of the semiconductor substrate 100 surrounded by the p-type diffusion layer 104 again to form a MOS gate structure and a necessary front-surface-side functional region is performed. The rear surface of the semiconductor substrate 100 is ground and removed such that the bottom of the p-type diffusion layer 104 is exposed, as represented by a dashed line, thereby reducing the thickness of the semiconductor substrate 100 (FIG. 6D and FIG. 7D). A rear surface structure including a p-type collector region and a collector electrode (which are not illustrated) is formed on the ground rear surface and the semiconductor substrate 100 is cut along a scribe line 108 which is disposed in a central portion of the p-type diffusion layer 104. The reverse blocking IGBT which is divided as a chip is illustrated in the cross-sectional views of FIG. 8A and FIG. 9.
However, as illustrated in FIGS. 6 and 7, in the reverse blocking IGBT in which the p-type separation layer is formed by coating diffusion or ion implantation, a high-temperature and long-term thermal diffusion process is needed in order to form a deep p-type separation layer as described above. As a result, during the high-temperature and long-term thermal diffusion process, an oxygen atom is introduced between the lattices in the semiconductor substrate. As a result, an oxygen precipitate is generated, the phenomenon in which oxygen is changed to a donor occurs, or a crystal defect occurs. When the crystal defect is introduced, there is a concern that the amount of leakage current will increase at the pn junction in the semiconductor substrate or the breakdown voltage and reliability of the insulating film formed on the semiconductor substrate will be significantly reduced.
In order to solve the problems caused by the high-temperature and long-term thermal diffusion process, a plurality of methods have been developed which reduce the diffusion depth of the p-type separation layer to shorten the time required for the high-temperature thermal diffusion process. For example, there is a method which forms a V-groove in the rear surface of a semiconductor substrate to reduce the depth of the separation layer, thereby shortening the time required for a high-temperature thermal diffusion process for forming a separation layer (for example, see U.S. Pat. No. 7,741,192 JP 2006-303410 A, and JP 2011-181770 A). FIG. 8B illustrates an example of the end structure of a reverse blocking IGBT produced by U.S. Pat. No. 7,741,192 JP 2006-303410 A, and JP 2011-181770 A. In addition, a method has been known which forms a trench 109 having a vertical side wall with a depth of 200 μm from the front surface of a semiconductor substrate 100 and forms a separation layer 104b with a small depth on the side wall, thereby reducing the time required for a high-temperature thermal diffusion process, as illustrated in the cross-sectional view of FIG. 11. FIG. 11 is a cross-sectional view illustrating the structure of a reverse blocking IGBT according to the related art including the separation layer which is formed using the trench. In FIG. 11, reference numeral 106 indicates a p-type collector region, reference numeral 108 indicates a scribe line, and reference numeral 110 indicates a MOS gate structure provided on the front surface side of a substrate.
In the related art, the semiconductor substrates which are used to produce high-breakdown-voltage power devices include a silicon semiconductor substrate (hereinafter, referred to as an FZ silicon semiconductor substrate) that is cut from a silicon single crystal (hereinafter, referred to as an FZ silicon single crystal) produced by a floating zone (FZ) method using polycrystalline silicon (hereinafter, referred to as FZ polycrystalline silicon). The FZ silicon semiconductor substrate has advantages that dislocation included in a crystal is small and the content of oxygen is small, as compared to a silicon semiconductor substrate (hereinafter, referred to as a CZ silicon semiconductor substrate) that is cut from a silicon single crystal (hereinafter, referred to as a CZ silicon single crystal) produced by a Czochralski (CZ) method. Therefore, the FZ silicon single crystal is particularly indispensable as a silicon crystal for a power device with a high breakdown voltage and high current capacity. An FZ silicon semiconductor substrate with a large diameter is required in order to reduce the costs of the device. However, it is difficult to increase the diameter of the FZ silicon semiconductor substrate, as compared to the CZ silicon semiconductor substrate.
In general, as described above, FZ polycrystalline silicon is used as a raw material for the FZ silicon single crystal. However, the FZ polycrystalline silicon which is needed as a raw material in the FZ method needs to have high purity, to be less likely to be cracked or broken, to have a uniform grain-boundary structure, to have a diameter suitable for the FZ silicon single crystal to be produced, and to have a cylindrical shape which is flat, has a large crank, and has a good surface state. The production yield and productivity of the FZ polycrystalline silicon are significantly less than those of nugget-shaped polycrystalline silicon (hereinafter, referred to as CZ polycrystalline silicon) used in the CZ method. There is an increasing demand for the CZ polycrystalline silicon with a diameter of 300 mm. A method has been known which produces an FZ silicon single crystal with a large diameter, using, as a raw material, a large-diameter CZ silicon single crystal which is stably obtained from polycrystalline silicon, instead of the FZ polycrystalline silicon according to the related art (for example, see the following JP 2007-314374 A). Hereinafter, a silicon semiconductor substrate which is cut from the FZ silicon single crystal produced by this method is referred to as a CZ-FZ silicon semiconductor substrate.
However, as described above, in the method disclosed in the above-mentioned U.S. Pat. No. 7,741,192 JP 2006-303410 A, and JP 2011-181770 A in which the V-groove is formed in the rear surface of the semiconductor substrate, the depth of the p-type diffusion layer 104a from the front surface of the substrate is reduced to reliably shorten the thermal diffusion time at a high temperature. However, when the depth of the p-type diffusion layer 104a is too small, another problem occurs. Specifically, when the depth of the diffusion layer 104a from the front surface of the substrate is reduced in order to shorten the thermal diffusion time at a high temperature, the depth of the V-groove needs to be increased by a value corresponding to the reduction in the depth. As a result, a new problem that the semiconductor substrate 100 is likely to be broken occurs.
In the method which forms the p-type separation layer 104b using the trench 109 with the side wall vertical to the main surface to reduce the thermal diffusion time at a high temperature as illustrated in FIG. 11, the following problem occurs. For example, when a typical dry etching device is used, the time required to etch each trench 109 with a depth of about 200 μm is about 100 minutes. Therefore, when the p-type separation layer 104b is formed using the trench 109, the lead time increases and the number of maintenances increases.
In the high-temperature and long-term thermal diffusion process described with reference to FIGS. 6 to 8, when the above-mentioned CZ-FZ silicon semiconductor substrate is used, the yield of the semiconductor device is reduced (lowered) by the influence of crystal defects which synergistically occur due to the vacancies that are included in the substrate at the beginning (before a semiconductor device producing process) and crystal defects which newly occur in the semiconductor substrate due to an atmosphere gas species during a thermal diffusion process, as compared to the case in which the FZ silicon semiconductor substrate according to the related art is used.